Triton 编译器发布: gfx950-tutorial-v2.1

来源摘要

Rebases the tutorial pin onto current upstream triton main (c349ce5), 340 commits ahead of the v1.1/v2.0 fork point. Two commits are carried; the warp-pipeline barrier commit from v2.0 is deliberately dropped (see below). [AMD] gfx950 tutorial: in-tree support for the out-of-tree LLIR-scheduler and amdgcnas plugins — TRITON_FORCE_MFMA_AGPR (sets amdgpu-mfma-vgpr-form=false) and LLVM_PASS_PLUGIN_KEEP_TARGET_MACHINE (keeps the TargetMachine so the plugin gets target-aware cost models). [Gluon] gl.warp_predicate — a per-wave masked-skip region lowering to s_and_saveexec + s_cbranch_execz, with no cross-wave reduction and no barrier. kernels/attention/fmha_v4.py does not compile without it. LLVM pin: 850a2b1 -> b010a18d. The out-of-tree LLIR-scheduler plugin IS ABI-locked to the LLVM pin and MUST be rebuilt; the v2.0 .so segfaults here. The plugin source needs no changes. DROPPED from v2.0: the warp-pipeline barrier commit (always-LOCAL cluster barriers, wrap-around barrier at the loop top, hard LDS drain). Upstream occupy the same code, and a correct merge needs the warp-pipeline dependency model rather than a mechanical conflict resolution. ConvertWarpPipeline.cpp is therefore pristine upstream at this tag. Known cost of that drop, measured on MI355X (rocprofv3 prepared launch, n=3, B=32 HQ=8 S=8192 D=128 bf16): fmha_v3 1249.9 -> 1200.1 (-4.0%), fmha_v4 1325.2 -> 1279.0 (-3.5%). GEMM is unaffected: intra_wave/a16w16 v9 at K=8192 fp16 measures 1349.7 vs 1349.4 on v2.0. Verified: both attention kernels produce bit-identical results across five runs and match v2.0's error exactly (7.84e-04 / 9.99e-04); all three inter_wave GEMM kernels (a16w16 fp16+bf16, a8w8, a4w4) pass every shape; and intra_wave/a16w16 v9 passes with the full llir + force-agpr + amdgcnas stack.